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march 2004 copyright ? alliance semiconductor. all rights reserved. ? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 1 of 23 2.5v 1m x 18 pipelined burst synchronous sram features ? organization: 1,048,576 x18 bits ? fast clock speeds to 166 mhz in lvttl/lvcmos ? fast clock to data access: 3.5/3.8 ns ?fast oe access time: 3.5/3.8 ns ? fully synchronous register-to-register operation ? dual -cycle deselect ? single-cycle deselect also available (as 7c251mpfs18a ) ? asynchronous output enable control ? available 100-pin tqfp and 165-ball bga packages ? byte write enables ? multiple chip enables for easy expansion ? 2.5v core power supply ? ntd? 1 pipelined architecture available (as7c251mntd18a, as7c25512ntd32a/ as7c25512ntd36a) ? boundary scan using ieee 1149.1 jtag function 1 ntd? is a trademark of allian ce semiconductor co rporation. all trademarks mentioned in th is document are the prop erty of their respective owners. logic block diagram selection guide -166 -133 units minimum cycle time 6 7.5 ns maximum clock frequency 166 133 mhz maximum clock access time 3.5 3.8 ns maximum operating current 290 270 ma maximum standby current 85 75 ma maximum cmos standby current (dc) 40 40 ma burst logic adv adsc adsp clk lbo clk clr cs 20 18 20 a[19:0] 20 address d q cs clk register 1m x 18 memory array 18 18 dqb clk dq byte write registers dqa clk dq byte write registers enable clk dq register enable clk dq delay register ce output registers input registers power down dq[a,b] 2 ce0 ce1 ce2 bw b bw a oe zz oe clk clk bwe gwe 18
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 2 of 23 pin and ball designations pin configuration for 100-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 lbo a a a a a1 a0 nc nc v ss v dd a a a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 nc nc bwb bwa ce2 v dd v ss clk gwe bwe oe adsc adsp adv a a tqfp 14 x 20mm a nc nc nc v ddq v ssq nc nc dqb0 dqb1 v ssq v ddq dqb2 dqb3 nc v dd nc v ss dqb4 dqb5 v ddq v ssq dqb6 dqb7 dqpb nc v ssq v ddq nc nc nc a nc nc v ddq v ssq nc dqpa dqa7 dqa6 v ssq v ddq dqa5 dqa4 v ss zz dqa3 dqa2 v ddq v ssq dqa1 dqa0 nc nc v ssq v ddq nc nc nc v dd nc
3/25/04, v. 1.0 alliance semiconductor 3 of 23 as7c251mpfd18a ? ball assignments for 165-ball bga 1m x 18 1 2 3 4 5 6 7 8 9 10 11 a nc a ce0 bwb nc ce2 bwe adsc adv aa b nc a ce1 nc bwa clk gwe oe adsp anc c nc nc vddq vss vss vss vss vss vddq nc dqpa d nc dqb vddq vdd vss vss vss vdd vddq nc dqa e nc dqb vddq vdd vss vss vss vdd vddq nc dqa f nc dqb vddq vdd vss vss vss vdd vddq nc dqa g nc dqb vddq vdd vss vss vss vdd vddq nc dqa h nc nc nc vdd vss vss vss vdd nc nc zz j dqb nc vddq vdd vss vss vss vdd vddq dqa nc k dqb nc vddq vdd vss vss vss vdd vddq dqa nc l dqb nc vddq vdd vss vss vss vdd vddq dqa nc m dqb nc vddq vdd vss vss nc vdd vddq dqa nc n dqpb nc vddq vss nc a vss vss vddq nc nc p nc nc a a tdi a1 1 1 a0 and a1 are the two least significant bits (lsb) of the addr ess field and set the internal bu rst counter if burst is desire d. tdoaaaa r lbo nc a a tms a0 1 tckaaaa
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 4 of 23 functional description the as7c251mpfd18a is a high-performance cm os 16-mbit synchronous static random ac cess memory (sram) device organized as 1,048,576 words x 18 bits and incorporates a two-stage register-register pipeline for highest frequency on any given technology . fast cycle times of 6/7.5 ns with clock access times (t cd ) of 3.5/3.8 ns enable 166 mhz and 133 mhz bus frequencies. three chip enable (ce ) inputs permit easy memory e xpansion. burst operation is initi ated in one of two ways: the controller addres s strobe (adsc ), or the processor address strobe (adsp ). the burst advance pin (adv ) allows subsequent internal ly generated bur st addresses. read cycles are initiated with adsp (regardless of we and adsc ) using the new external address clocked into the on-chip address register when adsp is sampled low, the chip enables are sampled active, and the output buffer is enabled with oe . in a read operation, the data accessed by the current address registered in the address registers by the positive edge of clk is carried to the data-out regi sters and driven on the output pins on the ne xt positive edge of clk. adv is ignored on the clock edge that samples adsp asserted, but it is sampled on all subsequent clock edges. address is incremented internally for the next access of the burst when adv is sampled low and both address strobes are high. burst mode is selectable with the lbo input. with lbo unconnected or driven high, bur st operations use an interleaved count sequence. with lbo driven low, the device us es a linear count sequence. write cycles are performed by disa bling the output buffers with oe and asserting a write command. a global write enable gwe writes all 18 bits regardless of the state of individual bw[a,b] inputs. alternately, when gwe is high, one or more bytes may be written by asserting bwe and the appropriate individual byte bwn signals. bwn is ignored on the clock edge that samples adsp low, but it is sampled on all subsequent cloc k edges. output buffers are disabled when bwn is sampled low, regardless of oe . data is clocked into the da ta input register when bwn is sampled low. address is incremented internally to the next burst address if bwn and adv are sampled low. read or write cycles may also be initiated with adsc instead of adsp . the differences between cycles initiated with adsc and adsp follow. ?adsp must be sampled high when adsc is sampled low to initiate a cycle with adsc . ?we signals are sampled on the clock edge that samples adsc low (and adsp high). ? master chip enable ce0 blocks adsp , but not adsc . the as7c251mpfd18a family operates from a co re 2.5v power supply. thes e devices are available in a 100-pin tqfp and 165-ball bg a. tqfp and bga capacitance tqfp and bga thermal resistance parameter symbol test conditions min max unit input capacitance c in v in = 0v - 5 pf i/o capacitance c i/o v in = v out -7pf description symbol typical units conditions thermal resistance (junction to ambient) 1 1 this parameter is sampled. 1 layer ja 40 c/w test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 4 layer ja 22 c/w thermal resistance (junction to top of case) 1 jc 8 c/w
3/25/04, v. 1.0 alliance semiconductor 5 of 23 as7c251mpfd18a ? signal descriptions write enable truth table (per byte) key: x = don?t care; l = low; h = high; b we , b wn = internal write signal signal i/o properties description clk i clock clock. all inputs except oe , zz, and lbo are synchronous to this clock. a,a0,a1 i sync address. sampled when all chip enables are active and when adsc or adsp are asserted. dq[a,b] i/o sync data. driven as output when the chip is enabled and when oe is active. ce0 i sync master chip enable. sample d on clock edges when adsp or adsc is active. when ce0 is inactive, adsp is blocked. refer to the ?synchronous truth table? for more information. ce1, ce2 i sync synchronous chip enables. active high and active low, respectively. sampled on clock edges when adsc is active or when ce0 and adsp are active. adsp i sync address strobe processor. asserted low to load a new bus address or to enter standby mode. adsc i sync address strobe controller. asserted low to load a new address or to enter standby mode. adv i sync advance. asserted low to continue burst read/write. gwe i sync global write enable. asserted low to wr ite all 32/36 and 18 bits. when high, bwe and bw[a,b] control write enable. bwe i sync byte write enable. asserted low with gwe high to enable effect of bw[a,b] inputs. bw[a,b] i sync write enables. used to control write of individual bytes when gwe is high and bwe is low. if any of bw[a,b] is active with gwe high and bwe low, the cycle is a write cycle. if all bw[a,b] are inactive, the cycle is a read cycle. oe i async asynchronous output enable. i/o pins are driven when oe is active and the chip is in read mode. lbo istatic selects burst mode. when tied to v dd or left floating, device follows interleaved burst order. when driven low, device follows linear burst order. this signal is internally pulled high. tdo o sync serial data-out to the jtag circuit. deli vers data on the negative edge of tck (bga only). tdi i sync serial data-in to the jtag circuit. sampled on the rising edge of tck (bga only). tms i sync this pin controls the test access port state machine. sampled on the rising edge of tck (bga only). tck o sync serial data-out to the jtag circuit. deli vers data on the negative edge of tck (bga only). zz i async sleep. places device in low power mode; da ta is retained. connect to gnd if unused. nc - - no connects function gwe bwe bwa bwb write all bytes (a, b) lxxx hlll write byte a h l l h write byte b h l h l read hhxx hlhh
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 6 of 23 burst sequence table synchronous truth table interleaved burst address linear burst address a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 1 st address 0 00 11 01 11 st address 0 00 11 01 1 2 nd address 0 10 01 11 02 nd address 0 11 01 10 0 3 rd address 1 01 10 00 13 rd address 1 01 10 00 1 4 th address 1 11 00 10 04 th address 1 11 00 11 0 ce0 1 1 x = don?t care, l = low, h = high ce1 ce2 adsp adsc adv write [2] 2 for write , l means any one or more byte write enable signals (bwa or bwb ) and bwe are low or gwe is low. write = high for all bwx , bwe , gwe high. see "write enable truth table (per byte)," on page 5 for more information. oe address accessed clk operation dq hxxxlx x x na l to h deselecthi ? z l l x l x x x x na l to h deselect hi ? z l l x h l x x x na l to h deselect hi ? z l x h l x x x x na l to h deselect hi ? z l x h h l x x x na l to h deselect hi ? z l h l l x x x l external l to h begin read q l h l l x x x h external l to h begin read hi ? z l h l h l x h l external l to h begin read q l h l h l x h h external l to h begin read hi ? z xxxhhl h l next l to hcontinue readq xxxhhl h h next l to hcontinue readhi ? z xxxhhh h l current l to hsuspend readq xxxhhh h h current l to hsuspend readhi ? z hxxxhl h l next l to hcontinue readq hxxxhl h h next l to hcontinue readhi ? z hxxxhh h l current l to hsuspend readq hxxxhh h h current l to hsuspend readhi ? z l h l h l x l x external l to h begin write d 3 3 for write operation following a read, oe must be high before the in put data set up time and held high throughout the input hold time xxxhhl l x next l to hcontinue writed hxxxhl l x next l to hcontinue writed xxxhhh l x current l to hsuspend writed hxxxhh l x current l to hsuspend writed
3/25/04, v. 1.0 alliance semiconductor 7 of 23 as7c251mpfd18a ? absolute maximum ratings note: stresses greater than those listed in this table may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implie d. exposure to absolute maximum rating conditions may affect reliability. recommended operating conditions parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.3 +3.6 v input voltage relative to gnd (input pins) v in ?0.3 v dd + 0.3 v input voltage relative to gnd (i/o pins) v in ?0.3 v ddq + 0.3 v power dissipation p d ?1.8w dc output current i out ?20 mama storage temperature (plastic) t stg ?65 +150 o c temperature under bias t bias ?65 +135 o c parameter symbol min nominal max unit supply voltage for inputs v dd 2.375 2.5 2.625 v supply voltage for i/o v ddq 2.375 2.5 2.625 v ground supply vss 0 0 0 v
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 8 of 23 dc electrical characteristics * i dd operating conditions and maximum limits parameter sym conditions min max unit input leakage current 1 1 lbo and zz pins and the 165 bga jtag pins (tms, tdi, and tck) ha ve an internal pull-up or pu ll-down, and input leakage = 10 a |i li |v dd = max, ov < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, ov < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 1.7 v dd +0.3 v i/o pins 1.7 v ddq +0.3 v input low (logic 0) voltage v il address and control pins -0.3 2 2 v il min = -1.5 for pulse width less than 0.2 x t cyc 0.7 v i/o pins -0.3 2 0.7 v output high voltage v oh i oh = ?4 ma, v ddq = 2.375v 1.7 ? v output low voltage v ol i ol = 8 ma, v ddq = 2.625v ? 0.7 v parameter sym conditions -166 -133 unit operating power supply current 1 1 i cc given with no output loading. i cc increases with faster cycle times and greater output loading. i cc ce0 = v il , ce1 = v ih , ce2 = v il , f = f max , i out = 0 ma 290 270 ma standby power supply current i sb deselected, f = f max , zz < v il 85 75 ma i sb1 deselected, f = 0, zz < 0.2v, all v in 0.2v or v dd ? 0.2v 40 40 i sb2 deselected, f = f max , zz ( v dd, v ddq ) ? 0.2v, all v in v il or v ih 40 40
3/25/04, v. 1.0 alliance semiconductor 9 of 23 as7c251mpfd18a ? timing characteristics over operating range parameter sym ?166 ?133 unit notes 1 1 see ?notes? on page 20. min max min max clock frequency f max ? 166 ? 133 mhz cycle time t cyc 6?7.5?ns clock access time t cd ?3.5?3.8ns output enable low to data valid t oe ?3.5?3.8ns clock high to output low z t lzc 0?0?ns2,3,4 data output invalid from clock high t oh 1.5?1.5? ns 2 output enable low to output low z t lzoe 0?0?ns2,3,4 output enable high to output high z t hzoe ? 3.5 - 3.8 ns 2,3,4 clock high to output high z t hzc ? 3.5 - 3.8 ns 2,3,4 output enable high to invalid output t ohoe 0?0?ns clock high pulse width t ch 2.4?2.4? ns 5 clock low pulse width t cl 2.3?2.4? ns 5 address setup to clock high t as 1.5?1.5? ns 6 data setup to clock high t ds 1.5?1.5? ns 6 write setup to clock high t ws 1.5 ? 1.5 ? ns 6,7 chip select setup to clock high t css 1.5 ? 1.5 ? ns 6,8 address hold from clock high t ah 0.5?0.5? ns 6 data hold from clock high t dh 0.5?0.5? ns 6 write hold from clock high t wh 0.5 ? 0.5 ? ns 6,7 chip select hold from clock high t csh 0.5 ? 0.5 ? ns 6,8 adv setup to clock high t advs 1.5?1.5? ns 6 adsp setup to clock high t adsps 1.5?1.5? ns 6 adsc setup to clock high t adscs 1.5?1.5? ns 6 adv hold from clock high t advh 0.5?0.5? ns 6 adsp hold from clock high t adsph 0.5?0.5? ns 6 adsc hold from clock high t adsch 0.5?0.5? ns 6
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 10 of 23 ieee 1149.1 serial boundary scan (jtag) the sram incorporates a serial boundary scan test access port (tap). the port operates in accordance with ieee standard 1149.1- 1990 but does not have the set of functions require d for full 1149.1 compliance. the inclusion of these functions would place an added d elay in the critical speed path of the sram. the tap controller functionality does not conflict with the ope ration of other devices using 1 149.1 fully compliant taps. it uses jedec-st andard 2.5v i/o logic levels. the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature if the jtag function is not being implemented, tck should be tied to vss, tms and tdi can be left unconnected , the device will come up in a reset state which will not interfere with th e operation of the device. tdo should be left unconnected. tap controller state diagram tap controller block diagram test access port (tap) test clock (tck) the test clock is used with only the tap controller. all inputs are captured on the ri sing edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tap controller receives commands from tms input. it is samp led on the rising edge of tck. yo u can leave this pin/ball uncon nected if the tap is not used. the pin/ball is pulled up internally, resulting in a logic high level. update-ir capture-ir shift-ir exit1-ir pause-ir exit2-ir select ir-scan update-dr capture-dr shift-dr exit1-dr pause-dr exit2-dr run-test/ idle test-logic reset select dr-scan 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 0 11 1 11 1 1 1 1 1 1 1 1 1 1 note: the 0 or 1 next to each state represents the value of tms at the rising edge of tck. selection circuitry selection circuitry 31 30 29 0 1 2 . . . boundary scan register 1 identification register bypass register instruction register x0 1 2 0 1 2 0 .. . .. tdi tms tck tdo tap controller 1 x = 53 for the x18 configuration, x = 72 for the x36 configuration.
3/25/04, v. 1.0 alliance semiconductor 11 of 23 as7c251mpfd18a ? test data-in (tdi) the tdi pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instr uction register, see the tap controller state diagra m. tdi is internally pulled up and can be unconne cted if the tap is unused in an application . tdi is connected to the most significant bit (msb) of any register. (see the tap controller block diagram.) test data-out (tdo) the tdo output pin/ball se rially clocks data-out from the registers. the out put is active depending upon the current state of t he tap state machine. the output changes on the falling e dge of tck. tdo is connected to the leas t significant bit (lsb) of any register. (s ee the tap controller state diagram.) performing a tap reset you can perform a reset by forcing tms high (v dd ) for five rising edges of tck. this rese t does not affect the operation of the sram and can be performed whil e the sram is operating. tap registers registers are connected between the tdi and t do pins/balls. they allow data to be scanne d into and out of the sram test circuit ry. only one register can be selected at a time thr ough the instruction register. da ta is serially loaded into the tdi pin/ball on the r ising edge of tck. data is output on the tdo pin/ba ll on the falling edge of tck. instruction register you can serially load three-bit instructions into the instruction register. the register is loaded when it is placed between th e tdi and tdo pins/balls as shown in the tap c ontroller block diagram. the instruction register is loaded with the idcode instruction at powe r up and also if the controller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two leas t significant bits are loaded with a binary ?01? pattern to all ow for fault isolation of the board-level series test data path. bypass register to save time when serially shifting data through registers, it is some times advantageous to skip certain chips. the bypass regi ster is a single- bit register that can be placed between the tdi and tdo pins/bal ls. this allows data to be sh ifted through the sram with minima l delay. the bypass register is set low (vss) when the by pass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bi directional pins/balls on the sram. the x36 configuration has a 72-bit-long register and the x18 configurat ion has a 53-bit-long register. the boundary scan register is loaded with the contents of the ra m i/o ring when the tap controller is in the capture-dr state a nd is then placed between the tdi and tdo pi ns/balls when the controller is moved to the shift-dr state. the extest, sample/reload, and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order table shows the orde r in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the most significant bit (msb) of the register is connect ed to tdi, and the least signifi cant bit (lsb) is connected t o tdo. identification (id) register the id register has a vendor code and othe r information described in the identificatio n register definitions table. the id regi ster is loaded with a vendor-specific, 32-bit code during th e capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram an d can be shifted out when the tap cont roller is in the shift-dr state.
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 12 of 23 tap instruction set eight different instructions are possible w ith the 3-bit instruction register. all combinations are listed in the instruction c odes table. three of these instructions are reserv ed and should not be used. note that the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 11 49.1 instructions are not fully implemented. the tap controller cannot be used to load addr ess, data, or control signals into the sr am and cannot preload the i/o buffers. the sram does not implement the 1149.1 co mmands extest or in test or the preload portion of sample/ preload. instead, it performs a capture of the i/o ring when th ese instructions are executed. instructions are loaded into the tap controller during the shift -ir state when the instruction register is placed between tdi a nd tdo. during this state, instructions are shifted thr ough the instruction register through the tdi and tdo pins/balls. to execute the instru ction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest the extest instruction, which executes whenever the instruction re gister is loaded with all 0s, is not implemented in this sram tap controller. the tap controller, ho wever, does recognize an all-0 in struction. when an extest instruction is loaded into the ins truction register, the sram responds as if a samp le/preload instruction has been loaded. unlike the sa mple/preload instruction, extest places the sram outputs in a high-z state. extest is a mandatory 1149.1 inst ruction. this device, therefore, is not compliant with 1149.1. idcode the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test log ic reset state. the idcode instruction causes a vendor-specific, 32- bit code to be loaded into the instru ction register. it al so places the ins truction register between the tdi and tdo pins/balls and allows the idcode to be shifted out of the device when the tap controller enters the shi ft-dr state. sample z the sample z instruction causes the boundary scan register to be connect ed between the tdi and tdo pi ns/balls when the tap cont roller is in a shift-dr state. it also plac es all sram outputs into a high-z state. sample/preload when the sample/preload instructio n is loaded into the instructi on register and the tap controller is in the capture-dr state, a snapshot of data on the inputs a nd bidirectional pins/balls is captured in the boundary scan register. note that the sample/pre load is a 1149.1 mandatory instruction, but the prelo ad portion of this instruction is not implem ented in this device. the tap controller , therefore, is not fully 1149.1 compliant. be aware that the tap controller clock can operate only at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the cl ock frequencies, it is possible that during the capture-dr state , an input or output can undergo a transition. the tap may then try to captur e a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable re sults may not be possible. to guarantee that the boundary sc an register captures the correct value of a si gnal, the sram signal must be stabilized long en ough to meet the tap controller?s captur e setup plus hold time ( t cs plus t ch). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is possible to capture all ot her signals and ignore the value of the ck and ck# captured in the boundary scan register. once the data is capt ured, it is possible to shift o ut the data by putting the tap into the shift-dr stat e. this places the boundary scan regi ster between the tdi and tdo pins. note that since the prel oad part of the command is not implemented, putting the tap to th e update-dr state while performing a sample/preload instruction wi ll have the same effect as the pause-dr command. bypass the advantage of the bypass instruction is that it shortens th e boundary scan path when multip le devices are connected together on a board. when the bypass instruction is loaded in the instruction register and the tap is plac ed in a shift-dr state, the bypass registe r is placed between tdi and tdo.
3/25/04, v. 1.0 alliance semiconductor 13 of 23 as7c251mpfd18a ? reserved do not use a reserved instruction.these instructions are not implemented but ar e reserved for future use. tap timing diagram tap ac electrical characteristics for notes 1 and 2, +10 o c < t j < +110 o c and +2.4v < v dd < +2.6v. description symbol min max units clock clock cycle time t thth 100 ns clock frequency f tf 10 mhz clock high time t thtl 40 ns clock low time t tlth 40 ns output times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 20 ns tdi valid to tck high t dvth 10 ns tck high to tdi invalid t thdx 10 ns setup times tms setup t mvth 10 ns capture setup t cs 1 1 t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2 test conditions are specified using th e load in the figu re tap ac output load equivalent. 10 ns hold times tms hold t thmx 10 ns capture hold t ch 1 10 ns 1 2 3456 t thtl t tlth t thth t mvth t thmx t dvth t thdx t tlox t tlov test clock (tck) test mode select (tms) tes t d ata - i n (tdi) tes t d ata - o u t (tdo) don?t care undefined
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 14 of 23 tap ac test conditions tap ac output load equivalent tap dc electrical characterist ics and operating conditions (+10 o c < t j < +110 o c and +2.4v < v dd < +2.6v unless otherwise noted) 1. all voltage referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 1.5v for t t khkh/2 undershoot: v il (ac) -0.5 for t t khkh/2 power-up: v ih +2.6v and v dd 2.4v and v ddq 1.4v for t 200ms during normal operation, v ddq must not exceed v dd . control input signals (such as ld , r/w , etc.) may not have pulsed widths less than t khkl (min) or operate at frequencies exceeding f kf (max). description conditions symbol min max units notes input high (logic 1) voltage v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current outputs disabled, 0v v in v ddq (dqx) il o -5.0 5.0 a output low voltage i olc = 100 av ol1 0.2 v 1 output low voltage i olt = 2ma v ol2 0.7 v 1 output high voltage i ohs = -100 av oh1 2.1 v 1 output high voltage i oht = -2ma v oh2 1.7 v 1 input pulse levels. . . . . . . . . . . . . . . vss to 2.5v input rise and fall times. . . . . . . . . . . . . . . 1 ns input timing reference levels. . . . . . . . . . 1.25v output reference levels . . . . . . . . . . . . . . 1.25v test load termination supply voltage. . . . 1.25v tdo 50 ? z o =50 ? 1.25v 20pf
3/25/04, v. 1.0 alliance semiconductor 15 of 23 as7c251mpfd18a ? identification re gister definitions scan register sizes instruction codes instruction field 1m x 18 description revision number (31:28) xxxx reserved for version number. device depth (27:23) xxxxx defines the depth of 1mb words. device width (22:18) xxxxx defines the width of x18 bits. device id (17:12) xxxxxx reserved for future use. jedec id code (11:1) 00001010010 allows unique identification of sram vendor. id register presence indicator (0) 1 indi cates the presence of an id register. register name bit size instruction 3 bypass 1 id 32 boundary scan x18:53 x36:72 instruction code description extest 000 captures i/o ring contents. places the boundary scan regi ster between tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan regi ster between tdi and tdo. forces all sram output dr ivers to a high-z state. reserved 011 do not use. this instruction is reserved for future use. sample/ preload 100 captures i/o ring contents. places the boundary scan regi ster between tdi and tdo. does not affect sram operation. this inst ruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use. this instruction is reserved for future use. reserved 110 do not use. this instruction is reserved for future use. bypass 111 places the bypass register be tween tdi and tdo. this op eration does not affect sram operations.
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 16 of 23 165-ball bga boundary scan order (x18) bit #s signal name ball id 1sa0 6r 2sa1 6p 3sa 4p 4sa 4r 5sa 3r 6 sa 3p 7 lbo 1r 8 dqpb 1n 9 dqb 1m 10 dqb 1l 11 dqb 1k 12 dqb 1j 13 nc 1h 14 dqb 2g 15 dqb 2f 16 dqb 2e 17 dqb 2d 18 sa 2b 19 sa 2a 20 ce0 3a 21 ce1 3b 22 bwb 4a 23 bwa 5b 24 ce2 6a 25 clk 6b 26 gwe 7b 27 bwe 7a bit #s signal name ball id 28 oe 8b 29 adsc 8a 30 adsp 9b 31 adv 9a 32 sa 10b 33 sa 10a 34 sa 11a 35 dqpa 11c 36 dqa 11d 37 dqa 11e 38 dqa 11f 39 dqa 11g 40 zz 11h 41 dqa 10j 42 dqa 10k 43 dqa 10l 44 dqa 10m 45 sa 11r 46 sa 10r 47 sa 10p 48 sa 9p 49 sa 9r 50 sa 8r 51 sa 8p 52 sa 6n 53 sa 11p *nc is don?t care
3/25/04, v. 1.0 alliance semiconductor 17 of 23 as7c251mpfd18a ? key to switching waveforms timing waveform of read cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. bw[a:b] is don?t care. *outputs are disabled within two clk cycles after dsel command undefined/don?t care falling input rising input ce1 t cyc t ch t cl t adsps t adsph t as t ah t ws t advs t oh clk adsp adsc address gwe , bwe ce0 , ce2 adv oe d out t css t hzc t cd t wh t advh t hzoe t adscs t adsch load new address adv inserts wait states q(a2y10) q(a2y11) q(a3) q(a2) q(a2y01) q(a3y01) q(a1) a2 a1 a3 t oe t lzoe t csh read q(a1) suspend read q(a1) read q(a2) burst read q(a 2y01 ) read q(a3) dsel* burst read q(a 2y10 ) suspend read q(a 2y10 ) burst read q(a 2y11 ) burst read q(a 3y01 ) burst read q(a 3y10 ) burst read q(a 3y11 ) q(a3y10) q(a3y11)
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 18 of 23 timing waveform of write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t cyc t cl t adsps t adsph t adscs t adsch t as t ah t ws t wh t css t advs t ds t dh clk adsp adsc address bwe ce0 , ce2 adv oe data in t csh t advh d(a2y01) d(a2y10) d(a3) d(a2) d(a2y01) d(a3y01) d(a3y10) d(a1) d(a2y11) adv suspends burst adsc loads new address a1 a2 a3 t ch ce1 bw[a:d] read q(a1) suspend write d(a1) read q(a2) suspend write d(a 2 ) adv burst write d(a 2y01 ) suspend write d(a 2y01 ) adv burst write q(a 2y10 ) write d(a 3 ) burst write d(a 3y01 ) adv burst write q(a 2y11 ) adv burst write d(a 3y10 )
3/25/04, v. 1.0 alliance semiconductor 19 of 23 as7c251mpfd18a ? timing waveform of read/write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t ch t cyc t cl t adsps t adsph t as t ah t ws t wh t advs t ds t dh t oh clk adsp address gwe ce0 , ce2 adv oe d in d out t lzc t advh t lzoe t oe t cd q(a1) q(a3y01) d(a2) q(a3) q(a3y10) q(a3y11) a1 a2 a3 ce1 t hzoe dsel suspend read q(a1) read q(a1) suspend write d(a 2 ) adv burst read d(a 3y01 ) suspend read q(a 3y11 ) adv burst read q(a 3y10 ) adv burst read q(a 3y11 ) read q(a2) read q(a3)
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 20 of 23 ac test conditions notes 1 for test conditions, see ?ac test conditions?, figures a, b, and c. 2 this parameter is measured with output load condition in figure c. 3 this parameter is sample d but not 100% tested. 4t hzoe is less than t lzoe , and t hzc is less than t lzc at any given temperature and voltage. 5t ch is measured as hi gh above vih, and t cl is measured as low below vil. 6 this is a synchronous device. all addresses must meet the specified setup and hold tim es for all rising edges of clk. all othe r synchronous inputs must meet the setup and hold times for all rising edges of cl k when chip is enabled. 7 write refers to gwe , bwe , and bw[a,b] . 8 chip select refers to ce0 , ce1 , and ce2 . z 0 = 50 ? d out 50 ? figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +2.5v ? output load: for t lzc , t lzoe , t hzoe , t hzc , see figure c. for al l others, see figure b. ? input pulse level: gnd to 2.5v. see figure a. ? input rise and fall time (measured at 0.25v and 2.25v): 2 ns. see figure a. ? input and output timing re ference levels: 1.25v. v l = v ddq /2 thevenin equivalent: 353 ?/1538? 5 pf* 319 ?/1667? d out gnd figure c: output load(b) *including scope and jig capacitance +2.5v
3/25/04, v. 1.0 alliance semiconductor 21 of 23 as7c251mpfd18a ? package dimensions 100-pin tqfp (quad flat pack) 165-ball bga (ball grid array) he e hd d b e tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.85 16.15 he 21.80 22.20 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters a1 a2 l1 l c / 0.450.05 (165x) ? 0.08 ? 0.15 6 7 8 9 10 11 1 2 3 4 5 6 5 4 3 2 111 10 9 8 7 h d f e g a c b m p n r j l k 13.000.10 10.00 1.00 15.000.10 14.00 1.00 15.000.10 13.000.10 a1 corner index area all measurements are in mm. min typ max a 1.00 b 14.90 15.00 15.10 c 14.00 d 12.90 13.00 13.10 e 10.00 f 0.26 g 0.30 0.35 0.40 h 1.20 i 0.40 0.45 0.50 z z xy 0.350.05 1.20 max 0.26 0.50 0.20 z top view bottom view side view detail of solder ball a b c a e d d f h g i h d f e g a c b m p n r j l k 0.12 z m m
? as7c251mpfd18a 3/25/04, v. 1.0 alliance semiconductor 22 of 23 ordering information note: add ?n? to the above part numbers for lead free parts (ex. as7c251mpfd18a-166tqcn) part numbering guide 1. alliance semiconductor sram prefix 2. operating voltage: 25 = 2.5v 3. organization: 1m 4. pipelined mode 5. deselect: d = double-cycle deselect 6. organization: 18 = x18 7. production version: a = first production version 8. clock speed (mhz) 9. package type: tq = tqfp; b = bga 10. operating temperature: c = commercial ( 0 c to 70 c); i = industrial ( -40 c to 85 c) 11. n = lead free part package & width ?166 ?133 tqfp x18 as7c251mpfd18a-166tqc as7c251mpfd18a-133tqc as7c251mpfd18a-166tqi as7c251mpfd18a-133tqi bga x18 as7c251mpfd18a-166bc AS7C251MPFD18A-133BC as7c251mpfd18a-166bi as7c251mpfd18a-133bi as7c 25 1m pf d 18 a ?xxx tq or b c/i x 1 23 45678 91011
? as7c251mpfd18a alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number: as7c251mpfd18a document version: v. 1.0 ? copyright 2003 alliance semic onductor corporation. all rights reserved. our th ree-point logo, our name and intelliwatt are tr ademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsib ility for any errors that may appear in this document. the da ta contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the inform ation in this product data sheet is intended t o be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or custome r. alliance does not assume any responsibility or liability arising out of the applicatio n or use of any product described herein, and disclaims any expr ess or implied warran ties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantab ility, or infringement of any intellectual property ri ghts, except as express agreed to in alliance's terms and conditions of sale (which ar e available from alliance). all sales of alliance products are ma de exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; m ask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alli ance does not authorize its products for use as critical compone nts in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to th e user, and the inclusion of alliance products in su ch life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. ?

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